Document Type: Research Paper
Islamic Azad University Central Tehran Branch
Department of Electrical and Electronics, Islamic Azad University, Central Tehran Branch, Tehran, Iran
Department of Electrical and Electronics, Islamic Azad University, Central Tehran Branch, , Tehran, Iran
The present study is to investigate and design the logic gates and half adder circuits by using multilayer neural network. The parallel function of the neural networks allows their application in designing high-speed circuits. DSP and FPGA can be used in implementation of these circuits, which reduces the area of the circuit. This study first considers logic gates, and since half adder circuits are the basic systems in computing, a half adder circuit is designed in this study. To design a full adder circuit, two half adders and an OR gate can be used. The results of this study are consistent with the results of gates designed with other technologies such as CMOS and TTL, except that neural networks use less power. The results of the simulations are consistent with the results of logic gates and half adder designed with CMOS and TTL technologies. Matlab 2017 has been used in this paper for simulation.